In electronic circuit applications supporting high-voltage switching operations, a circuit called a level shifter is employed to transfer signals between circuit networks having different voltage levels. A level shifter functions to convert a logic signal operating in a voltage range from 0 to V1 into an output signal operating in a voltage range from 0 to V2 when it is combined with an inverter.
Furthermore, a level shifter also refers to a circuit for simply transferring a voltage level rather than transferring a logic signal. In this case, if a specific logic condition is satisfied, the level shifter transfers a voltage level from an input side to an output side via a pass switch, and then may perform the operation of boosting or stepping down voltage using a circuit, such as a bootstrap or a charge pump.
Examples of the typical circuit of such a high-voltage level shifter are disclosed in U.S. Pat. No. 5,160,854 entitled “Single-Drive Level Shifter with Low Dynamic Impedance” and U.S. Pat. No. 6,727,742 entitled “High-Voltage Level Shifting Circuit with Optimized Response Time.”
U.S. Pat. No. 6,727,742 discloses an example of the typical conventional circuit of a high-voltage level shifter, which is illustrated in FIG. 1.
Referring to FIG. 1, a level shifter circuit is illustrated in which an output voltage OUT swings between VBOOT and VPHASE in response to an input control signal ϕ.
VBOOT, that is, the upper limit of the output voltage VOUT, is high-voltage power that is commonly equal to or higher than 40-50 V, and VPHASE, that is, the lower limit of the output voltage VOUT, is power that has a voltage level lower than VBOOT by a specific difference. Generally, a high-voltage level shifter is widely used in power devices for handling high currents. When a power device is implemented using a semiconductor, a double diffused MOS (DMOS) transistor is widely used.
DMOS transistors are classified into vertical diffusion-type vertical DMOS (VDMOS) transistors and lateral diffusion-type lateral DMOS (LDMOS) transistors. It is known that for both VDMOS and LDMOS transistors, a drain-source breakdown voltage is a high voltage ranging from 40 to 50 V and a gate-source voltage is determined by the thickness of the channel oxide of a corresponding transistor, so that it is very difficult to increase the gate-source voltage to a level of tens of volts.
Accordingly, a high-voltage level shifter is designed not to exceed the limit of a gate-source voltage in order to ensure the safe operation of a DMOS transistor. For example, in FIG. 1, when the limit of the gate-source voltage of the DMOS transistor is 10 V, the difference between VBOOT and VPHASE is determined to be within 10 V.
In order to obtain an electric potential VPHASE having a specific difference with VBOOT, the combination of a resistor R1 and a current source Idd and a clamping circuit M3 are widely used, as illustrated in FIG. 1.
When an input control signal ϕ is turned on, the current source Idd operates, a switch MHV is turned on, and thus current Idd flows through the switch MHV. In this case, all or part of the current Idd flows through the resistor R1, and thus a difference in voltage between VBOOT and a node X 110 is generated by a voltage drop between both terminals of the resistor R1. Since the voltage of the node X 110 is the voltage Vg of the gate nodes of M1 and M2, M1, that is, a PMOS transistor, is turned on and an output voltage OUT has the voltage level of VBOOT. Meanwhile, when the transistor M3 is turned on, a difference corresponding to the threshold voltage VT,M3 of the transistor M3 is present between the voltage VPHASE of the gate node of M3 and the voltage Vx of the node X 110, that is, the source node of M3. That is, a condition, such as that of Equation 1, is satisfied:Vx=VPHASE−VT,M3  (1)
When a potential difference between VPHASE and Vx reaches VT,M3, the transistor M3 is turned off, and thus the current Idd flows only through the resistor R1. In this case, the voltage Vx of the node X 110 satisfies the condition of Equation 2 below:Vx=VBOOT−Idd·R1  (2)
As a result, VPHASE, that is, the lower limit of the output voltage OUT, satisfies Equation 3 below:VPHASE=VBOOT−Idd·R1+VT,M3  (3)
That is, it can be seen that the difference between VPHASE, that is, the lower limit of the output voltage VOUT, and VBOOT is determined by the threshold voltage VT,M3 of the current source Idd, the resistor R1 and the transistor M3.
In contrast, when the input control signal ϕ is turned off, the current source Idd is cut off. In this case, when a sufficient time has elapsed, current flowing through the resistor R1 becomes 0, and thus voltage across both terminals of the resistor R1 becomes 0 V. That is, Vx=VBOOT. In this case, the drain-source voltage of the transistor M3 is 0 V, and current does not still flow through the transistor M3. In this case, since the voltage of Vx is VBOOT, which is high, the transistor M2 is turned on, and the output voltage OUT has the voltage level of VPHASE.
Although the circuit of FIG. 1 will operate in the above-described manner when observed over a long period of time, the circuit is problematic in that in practice, the operation thereof is delayed by the parasitic capacitances Cr and Cp of the node X 110 illustrated in FIG. 1. In this case, Cr denotes the parasitic capacitance of the resistor R1, and Cp denotes the parasitic capacitance of the switch MHV.
When the input control signal ϕ is turned on in an off state, the voltage Vx of the node X 110 should drop from VBOOT to (VBOOT−Idd·R1), but operates slowly with an RC delay based on a time constant R1·(Cr+Cp) in this process. In the same manner, when the input control signal ϕ is turned off in an on state, the voltage Vx of the node X 110 should rise from (VBOOT−Idd·R1) to VBOOT, but in this process, Vx slowly reaches a steady state due to the time constant R1·(Cr+Cp).
This means that a transient response is considerably extended. In this case, if Vx has an intermediate level between VBOOT and VPHASE, there is the risk of the voltage of VPHASE changing to a value close to VBOOT for various reasons, such as the event that the transistors M1 and M2 are simultaneously turned on. In order to avoid this problem, the inconvenience of design in which reservoir capacitance corresponding to the node of VPHASE should be very high is incurred.
FIG. 2 is a diagram illustrating an improvement over the circuit of FIG. 1 presented in U.S. Pat. No. 6,727,742.
Referring to FIG. 2, the gate node of a clamping transistor M3 is connected to an output voltage OUT, other than VPHASE. Accordingly, when an input control signal ϕ has been maintained in an on state for a long time, Vx is clamped to VBOOT, that is, the voltage level of the output voltage OUT, other than VPHASE. That is, Equation 4 below is satisfied:Vx=VBOOT−VT,M3  (4)
This results in the effect in which the swing range of Vx becomes narrower than Idd·R1 of FIG. 1, and thus the switching speed of the level shifter increases.
However, despite the improved circuit of FIG. 2, a problem still exists in that the node X 110 suffers from a time response delay attributable to an RC time constant.
Furthermore, it is more difficult to match the threshold voltage characteristics of the transistors M1, M2 and M3 in the improved circuit of FIG. 2 than in the circuit of FIG. 1.
As a result, there is a demand for a circuit design technique that is capable of overcoming a time response delay attributable to an RC time constant while effectively protecting a transistor in a high-voltage switching circuit or a level shifting circuit as in the conventional technology.